1. Field of the Invention
The present invention relates to phase-locked loops (PLL) and, in particular, to a digital phase-locked loop that utilizes a high resolution tapped delay line to synchronize a generated clock signal to an external clock.
2. Discussion of the Prior Art
A phase-locked loop (PLL) is a circuit that generates a periodic signal that is synchronized to an external clock. Most PLLs include an internal oscillator circuit that operates at a frequency much higher than that of the external clock. A phase detector circuit identifies the direction and extent of the phase error between the internally generated clock and the external clock. An adjustment unit then utilizes the phase error to control the phase of the generated clock.
In some PLLs, phase adjustment is accomplished utilizing a voltage controlled oscillator (VCO), i.e. by controlling the frequency and phase of the generated clock signal utilizing voltage (or voltage that is converted to current). In a partial digital PLL, the phase detector is digital, while phase control is performed by a VCO. In an all-digital PLL, phase control is accomplished in one of the following ways: (1) a high frequency counter counts complete cycles of the input clock until it asserts the desired clock signal, (2) one output is selected from a tapped delay line to generate the desired clock signal based on the measured phase error, or (3) a combination of a tapped delay line and a counter is used for both course and fine tuning of the phase shift, respectively.
Using a counter requires an internal clock with a frequency that is much higher than the input signal rate. The limits on the frequency of the internal clock define the input frequency limits (typically on the order of tenths of Hz). Thus, the use of this type of PLL is restricted to low rate applications such as subcarrier demodulation or, alternatively, requires a very high frequency clock (up to 300 MHz is reported using ECL technology).
In a conventional tapped delay line PLL, the resolution of the delay line is too low for effective use in many current applications.